66. What is the hold condition of a flip-flop?
(a) both S and R inputs activated
(b) no active S or R input
(c) only S is active
(d) only R is active
67. Why are the S and R inputs of a gated flip-flop said to be synchronous?
(a) They must occur with the gate.
(b) Th
(c)
(d)
68. When is a flip-flop said to be transparent?
(a) when the Q output is opposite the input
(b) when the Q output follows the input
(c)
(d)
69. Which of the following is correct for a gated D flip-flop?
(a) The output toggles if one of the inputs is held HIGH.
(b) Only one of the inputs can be HIGH at a time.
(c) The output complement follows the input when enabled.
(d) Q output follows the input D when the enable is HIGH.
70. Edge-triggered flip-flops must have:
(a) very fast response times
(b) at least two inputs to handle rising and falling edges
(c) positive edge-detection circuits
(d) negative edge-detection circuits
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555555555571. Which of the following describes the operation of a positive edge-triggered D flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
5555555555 40. Which of the following describes the operation of a positive edge-triggered D-type flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
101. A 555 operating as a monostable multivibrator has a C1 = 100 F. Determine R1 for a pulse width of 500 ms. (a) 45 (b) 455 (c) 4.5 k (d) 455 k 102. Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________. (a) set (b) reset (c) latch (d) toggle 103. The postponed symbol () on the output of a flip-flop identifies it as being ________. (a) a D flip-flop (b) a J-K flip-flop (c) pulse triggered (d) trailing edge-triggered 104. Most people would prefer to use ________ over HDL. (a) graphic descriptions (b) functions (c) VHDL (d) AHDL 105. When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________. (a) S = 1, R = 1 (b) S = 1, R = 0 (c) S = 0, R = 1 (d) S = 0, R = 0 106. The key to edge-triggered sequential circuits in VHDL is the ________. (a) ARCHITECTURE (b) PROCESS (c) FUNCTION (d) VARIABLE 107. The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as a ________.…
555555555534. Which of the following is correct for a gated D-type flip-flop? (a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW. (b) The output complement follows the input when enabled. (c) Only one of the inputs can be HIGH at a time. (d) The output toggles if one of the inputs is held HIGH.