Flip Flops – Exercise – 2

61. On a master-slave flip-flop, when is the master enabled?

(a) when the gate is LOW
(b) when the gate is HIGH
(c) both of the above
(d) neither of the above

Answer
Answer : (b)
Explanation
Explanation : No answer description available for this question.Let us discuss.
Discuss
Discuss : Write your answer. Click here.

62. If an input is activated by a signal transition, it is ________.

(a) edge-triggered
(b) toggle triggered
(c) clock triggered
(d) noise triggered

Answer
Answer : (a)
Explanation
Explanation : No answer description available for this question.Let us discuss.
Discuss
Discuss : Write your answer. Click here.

63. What does the triangle on the clock input of a J-K flip-flop mean?

(a) level enabled
(b) edg
(c)
(d)

Answer
Answer : (b)
Explanation
Explanation : No answer description available for this question.Let us discuss.
Discuss
Discuss : Write your answer. Click here.

64. With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?

(a) 16
(b) 8
(c) 4
(d) 2

Answer
Answer : (b)
Explanation
Explanation : No answer description available for this question.Let us discuss.
Discuss
Discuss : Write your answer. Click here.

65. The output of a gated S-R flip-flop changes only if the:

(a) flip-flop is set
(b) control input data has changed
(c) flip-flop is reset
(d) input data has no change

Answer
Answer : (b)
Explanation
Explanation : No answer description available for this question.Let us discuss.
Discuss
Discuss : Write your answer. Click here.

Related Posts

  • Flip Flops - 71555555555571. Which of the following describes the operation of a positive edge-triggered D flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
    Tags: clock, output, flip-flop, inputs, input, low, high, electronics, engineering
  • Flip Flops - 405555555555 40. Which of the following describes the operation of a positive edge-triggered D-type flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
    Tags: output, clock, flip-flop, inputs, input, low, high, electronics, engineering
  • Flip Flops - 90555555555590. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________. (a) constantly LOW (b) constantly HIGH (c) a 20 kHz square wave (d) a 10 kHz square wave
    Tags: flip-flop, clock, input, output, low, high, electronics, engineering
  • Flip Flops - Exercise - 3101. A 555 operating as a monostable multivibrator has a C1 = 100 F. Determine R1 for a pulse width of 500 ms. (a) 45 (b) 455 (c) 4.5 k (d) 455 k 102. Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________. (a) set (b) reset (c) latch (d) toggle 103. The postponed symbol () on the output of a flip-flop identifies it as being ________. (a) a D flip-flop (b) a J-K flip-flop (c) pulse triggered (d) trailing edge-triggered 104. Most people would prefer to use ________ over HDL. (a) graphic descriptions (b) functions (c) VHDL (d) AHDL 105. When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________. (a) S = 1, R = 1 (b) S = 1, R = 0 (c) S = 0, R = 1 (d) S = 0, R = 0 106. The key to edge-triggered sequential circuits in VHDL is the ________. (a) ARCHITECTURE (b) PROCESS (c) FUNCTION (d) VARIABLE 107. The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as a ________.…
    Tags: flip-flop, output, clock, high, inputs, input, low, pulse, electronics, engineering
  • Flip Flops - 34555555555534. Which of the following is correct for a gated D-type flip-flop? (a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW. (b) The output complement follows the input when enabled. (c) Only one of the inputs can be HIGH at a time. (d) The output toggles if one of the inputs is held HIGH.
    Tags: output, high, input, inputs, low, flip-flop, electronics, engineering

LEAVE A REPLY

Please enter your comment!
Please enter your name here