71. Which of the following describes the operation of a positive edge-triggered D flip-flop?
(a) If both inputs are HIGH, the output will toggle.
(b) The output will follow the input on the leading edge of the clock.
(c) When both inputs are LOW, an invalid state exists.
(d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
72. What is the difference between the enable input of the 7472 and the clock input of the 7474?
(a) The 7472 is edge-triggered.
(b)
(c)
(d)
73. What is one disadvantage of an S-R flip-flop?
(a) It has no enable input.
(b) It has an invalid state.
(c) It has no clock input.
(d) It has only a single output.
74. If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?
(a) No change will occur in the output.
(b) An invalid state will exist.
(c) The output will toggle.
(d) The output will reset.
75. For an S-R flip-flop to be set or reset, the respective input must be:
(a) installed with steering diodes
(b) in parallel with a limiting resistor
(c) LOW
(d) HIGH
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