81. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.
(a) SET
(b) RESET
(c) clear
(d) invalid
82. An invalid condition in the operation of an active-HIGH input S-R latch occurs when ________.
(a) HIGHs are applied simultaneously to both inputs S and R
(b) LOWs are applied simultaneously to both inputs S and R
(c) a LOW is applied to the S input while a HIGH is applied to the R input
(d) a HIGH is applied to the S input while a LOW is applied to the R input
83. The symbols on this flip-flop device indicate ________.
(a) triggering takes place on the negative-going edge of the CLK pulse
(b) triggering takes place on the positive-going edge of the CLK pulse
(c) triggering can take place anytime during the HIGH level of the CLK waveform
(d) triggering can take place anytime during the LOW level of the CLK waveform
84. An RC circuit used in a nonretriggerable 74121 one-shot has an REXT of 49 k and a CEXT of 0.2 F. The pulse width (tW) is approximately ________.
(a) 6.9 s
(b) 6.9 ms
(c) 69 ms
(d) 690 ms
85. The pulse width of a one-shot circuit is determined by ________.
(a) a resistor and capacitor
(b) two resistors
(c) two capacitors
(d) none of the above
Related Posts
555555555571. Which of the following describes the operation of a positive edge-triggered D flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.- 5555555555 40. Which of the following describes the operation of a positive edge-triggered D-type flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
- 555555555590. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________. (a) constantly LOW (b) constantly HIGH (c) a 20 kHz square wave (d) a 10 kHz square wave
- 101. A 555 operating as a monostable multivibrator has a C1 = 100 F. Determine R1 for a pulse width of 500 ms. (a) 45 (b) 455 (c) 4.5 k (d) 455 k 102. Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________. (a) set (b) reset (c) latch (d) toggle 103. The postponed symbol () on the output of a flip-flop identifies it as being ________. (a) a D flip-flop (b) a J-K flip-flop (c) pulse triggered (d) trailing edge-triggered 104. Most people would prefer to use ________ over HDL. (a) graphic descriptions (b) functions (c) VHDL (d) AHDL 105. When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________. (a) S = 1, R = 1 (b) S = 1, R = 0 (c) S = 0, R = 1 (d) S = 0, R = 0 106. The key to edge-triggered sequential circuits in VHDL is the ________. (a) ARCHITECTURE (b) PROCESS (c) FUNCTION (d) VARIABLE 107. The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as a ________.…
- 555555555534. Which of the following is correct for a gated D-type flip-flop? (a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW. (b) The output complement follows the input when enabled. (c) Only one of the inputs can be HIGH at a time. (d) The output toggles if one of the inputs is held HIGH.