Flip Flops – Exercise – 2

96. An RC circuit used in a 74122 retriggerable one-shot has an REXT of 100 k and a CEXT of 0.005 F. The pulse width is ________.

(a) 70 s
(b) 16 s
(c) 160 s
(d) 32 s

Answer
Answer : (c)
Explanation
Explanation : No answer description available for this question.Let us discuss.
Discuss
Discuss : Write your answer. Click here.

97. A 555 operating as a monostable multivibrator has a C1 = 0.01 F. Determine R1 for a pulse width of 2 ms.

(a) 200 k
(b) 182 k
(c) 91 k
(d) 182

Answer
Answer : (b)
Explanation
Explanation : No answer description available for this question.Let us discuss.
Discuss
Discuss : Write your answer. Click here.

98. The output pulse width of a 555 monostable circuit with R1 = 4.7 k and C1 = 47 F is ________.

(a) 24 s
(b) 24 ms
(c) 243 ms
(d) 243 s

Answer
Answer : (c)
Explanation
Explanation : No answer description available for this question.Let us discuss.
Discuss
Discuss : Write your answer. Click here.

99. In a 555 timer, three 5 k resistors provide a trigger level of ________.

(a) 1/4 VCC and a threshold level 1/2 VCC
(b) 1/3 VCC and a threshold level 3/4 VCC
(c) 1/3 VCC and a threshold level 2/3 VCC
(d) 1/4 VCC and a threshold level 2/3 VCC

Answer
Answer : (c)
Explanation
Explanation : No answer description available for this question.Let us discuss.
Discuss
Discuss : Write your answer. Click here.

100. A 555 operating as a monostable multivibrator has an R1 of 1 M. Determine C1 for a pulse width of 2 s.

(a) 1.8 F
(b) 18 F
(c) 18 pF
(d) 18 nF

Answer
Answer : (a)
Explanation
Explanation : No answer description available for this question.Let us discuss.
Discuss
Discuss : Write your answer. Click here.

Related Posts

  • Flip Flops - 71555555555571. Which of the following describes the operation of a positive edge-triggered D flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
    Tags: clock, output, flip-flop, inputs, input, low, high, electronics, engineering
  • Flip Flops - 405555555555 40. Which of the following describes the operation of a positive edge-triggered D-type flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
    Tags: output, clock, flip-flop, inputs, input, low, high, electronics, engineering
  • Flip Flops - 90555555555590. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________. (a) constantly LOW (b) constantly HIGH (c) a 20 kHz square wave (d) a 10 kHz square wave
    Tags: flip-flop, clock, input, output, low, high, electronics, engineering
  • Flip Flops - Exercise - 3101. A 555 operating as a monostable multivibrator has a C1 = 100 F. Determine R1 for a pulse width of 500 ms. (a) 45 (b) 455 (c) 4.5 k (d) 455 k 102. Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________. (a) set (b) reset (c) latch (d) toggle 103. The postponed symbol () on the output of a flip-flop identifies it as being ________. (a) a D flip-flop (b) a J-K flip-flop (c) pulse triggered (d) trailing edge-triggered 104. Most people would prefer to use ________ over HDL. (a) graphic descriptions (b) functions (c) VHDL (d) AHDL 105. When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________. (a) S = 1, R = 1 (b) S = 1, R = 0 (c) S = 0, R = 1 (d) S = 0, R = 0 106. The key to edge-triggered sequential circuits in VHDL is the ________. (a) ARCHITECTURE (b) PROCESS (c) FUNCTION (d) VARIABLE 107. The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as a ________.…
    Tags: flip-flop, output, clock, high, inputs, input, low, pulse, electronics, engineering
  • Flip Flops - 34555555555534. Which of the following is correct for a gated D-type flip-flop? (a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW. (b) The output complement follows the input when enabled. (c) Only one of the inputs can be HIGH at a time. (d) The output toggles if one of the inputs is held HIGH.
    Tags: output, high, input, inputs, low, flip-flop, electronics, engineering

LEAVE A REPLY

Please enter your comment!
Please enter your name here