86. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.
(a) the clock pulse is LOW
(b) the clock pulse is HIGH
(c) the clock pulse transitions from LOW to HIGH
(d) the clock pulse transitions from HIGH to LOW
87. With regard to a D latch, ________.
(a) the Q output follows the D input when EN is LOW
(b) the Q output is opposite the D input when EN is LOW
(c) the Q output follows the D input when EN is HIGH
(d) the Q output is HIGH regardless of EN’s input state
88. A positive edge-triggered D flip-flop will store a 1 when ________.
(a) the D input is HIGH and the clock transitions from HIGH to LOW
(b) the D input is HIGH and the clock transitions from LOW to HIGH
(c) the D input is HIGH and the clock is LOW
(d) the D input is HIGH and the clock is HIGH
89. A J-K flip-flop is in a “no change” condition when ________.
(a) J = 1, K = 1
(b) J = 1, K = 0
(c) J = 0, K = 1
(d) J = 0, K = 0
90. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.
(a) constantly LOW
(b) constantly HIGH
(c) a 20 kHz square wave
(d) a 10 kHz square wave
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