51. How many flip-flops are required to produce a divide-by-128 device?
(a) 1
(b) 4
(c) 6
(d) 7
52. Propagation delay time, tPLH, is measured from the ________.
(a) triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
(b) triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
(c) preset input to the LOW-to-HIGH transition of the output
(d) clear input to the HIGH-to-LOW transition of the output
53. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?
(a) The logic level at the D input is transferred to Q on NGT of CLK.
(b) The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
(c) The Q output is ALWAYS identical to the D input when CLK = PGT.
(d) The Q output is ALWAYS identical to the D input.
54. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
(a) 10.24 kHz
(b) 5 kHz
(c) 30.24 kHz
(d) 15 kHz
55. What is the difference between the 7476 and the 74LS76?
(a) the 7476 is master-slave, the 74LS76 is master-slave
(b) the 7476 is edge-triggered, the 74LS76 is edge-triggered
(c) the 7476 is edge-triggered, the 74LS76 is master-slave
(d) the 7476 is master-slave, the 74LS76 is edge-triggered
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