5555555555
69. Which of the following is correct for a gated D flip-flop?
(a) The output toggles if one of the inputs is held HIGH.
(b) Only one of the inputs can be HIGH at a time.
(c) The output complement follows the input when enabled.
(d) Q output follows the input D when the enable is HIGH.
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books
|
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
5555555555112. Which of the following is correct for a D latch? (a) The output toggles if one of the inputs is held HIGH. (b) Q output follows the input D when the enable is HIGH. (c) Only one of the inputs can be HIGH at a time. (d) The output complement follows the input when enabled.- 555555555534. Which of the following is correct for a gated D-type flip-flop? (a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW. (b) The output complement follows the input when enabled. (c) Only one of the inputs can be HIGH at a time. (d) The output toggles if one of the inputs is held HIGH.
- 555555555568. When is a flip-flop said to be transparent? (a) when the Q output is opposite the input (b) when the Q output follows the input (c) (d)
- 555555555512. The output of an OR gate is LOW when ________. (a) all inputs are LOW (b) any input is LOW (c) any input is HIGH (d) all inputs are HIGH
- 5555555555117. What is one disadvantage of an S-R flip-flop? (a) It has no enable input. (b) It has an invalid state. (c) It has no clock input. (d) It has only a single output.