36. The truth table for an S-R flip-flop has how many VALID entries?
(a) 3
(b) 1
(c) 4
(d) 2
37. One example of the use of an S-R flip-flop is as a(n):
(a) transition pulse generator
(b) astable oscillator
(c) racer
(d) switch debouncer
38. If both inputs of an S-R NAND latch are LOW, what will happen to the output?
(a) The output would become unpredictable.
(b) The output will toggle.
(c) The output will reset.
(d) No change will occur in the output.
39. What is one disadvantage of an S-R flip-flop?
(a) It has no Enable input.
(b) It has a RACE condition.
(c) It has no clock input.
(d) It has only a single output.
40. Which of the following describes the operation of a positive edge-triggered D-type flip-flop?
(a) If both inputs are HIGH, the output will toggle.
(b) The output will follow the input on the leading edge of the clock.
(c) When both inputs are LOW, an invalid state exists.
(d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
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