41. Edge-triggered flip-flops must have _________.
(a) very fast response times
(b) at least two inputs to handle rising and falling edges
(c) a positive-transition pulse generator
(d) a negative-transition pulse generator
42. An S-R NAND latch with both of its inputs LOW has an output that is _____________.
(a) unpredictable
(b) floating
(c) HIGH
(d) LOW
43. An S-R flip-flop can be triggered by ______, ______, or ________.
(a) HIGHs, LOWs, PRESETs
(b) edges, levels, pulses
(c) HIGHs, LOWs, CLEARs
(d) SETs, RESETs, HIGHs
44. One example of the use of an S-R flip-flop is as a(n) _________.
(a) racer
(b) binary storage register
(c) astable oscillator
(d) transition pulse generator
45. For an S-R flip-flop to be SET or RESET, the respective input must be __________.
(a) LOW
(b) HIGH
(c) installed with steering diodes
(d) in parallel with a limiting resistor
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