21. If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse?
(a) 11101011
(b) 00010111
(c) 11110000
(d) 00000000
22. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________.
(a) 16 s
(b) 8 s
(c) 4 s
(d) 2 s
23. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
(a) 1100
(b) 0011
(c) 0000
(d) 1111
24. To serially shift a nibble (four bits) of data into a shift register, there must be ________.
(a) one clock pulse
(b) four clock pulses
(c) eight clock pulses
(d) one clock pulse for each 1 in the data
25. How much storage capacity does each stage in a shift register represent?
(a) One bit
(b) Two bits
(c) Four bits (one nibble)
(d) Eight bits (one byte)
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