30. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________.
(a) 0000 (b) 1111 (c) 0111 (d) 1000
Answer
Answer : (c)
Explanation
Explanation : No answer description available for this question. Let us discuss.
Shift Registers » Exercise - 124. To serially shift a nibble (four bits) of data into a shift register, there must be ________. (a) one clock pulse (b) four clock pulses (c) eight clock pulses (d) one clock pulse for each 1 in the data
Shift Registers » Exercise - 117. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________. (a) 1110 (b) 0111 (c) 1000 (d) 1001
Shift Registers » Exercise - 118. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________. (a) 1110 (b) 0001 (c) 1100 (d) 1000
Shift Registers » Exercise - 122. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________. (a) 16 s (b) 8 s (c) 4 s (d) 2 s
Shift Registers » Exercise - 143. What is meant by parallel load of a shift register? (a) All FFs are preset with data. (b) Each FF is loaded with data, one (c) (d)