Shift Registers – 30

Shift Registers » Exercise – 1

30. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________.

(a) 0000
(b) 1111
(c) 0111
(d) 1000

Answer
Answer : (c)
Explanation
Explanation : No answer description available for this question. Let us discuss.
Subject Name : Electronics Engineering
Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT
Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant
Electronics & Communication Engineering Books

Sale
Question Bank On Electronics & Communication Engineering
Highlight important details or key points; Summarize information in a clear and concise manner
₹ 317
Sale
A Handbook for Electronics Engineering(Old Edition)
Made Easy Editorial Board (Author); Marathi (Publication Language); 620 Pages - 01/01/2015 (Publication Date) - Made Easy Publications (Publisher)
₹ 320
Basic Electronic Devices and Circuits
Patil (Author); English (Publication Language)
Sale
Electronic Circuits: Analysis and Design (SIE) | 3rd Edition
Neamen, Donald (Author); English (Publication Language); 1351 Pages - 08/25/2006 (Publication Date) - McGraw Hill Education (Publisher)
₹ 2,000

GATE 2023 Total InfoENGG DIPLOMAUGC NET Total Info
IES 2023 Total InfoPSUs 2022 Total InfoCSIR UGC NET Total Info
JAM 2023 Total InfoM TECH 2023 Total InfoRAILWAY 2022 Total Info

Related Posts

  • Shift Registers - 24Shift Registers » Exercise - 124. To serially shift a nibble (four bits) of data into a shift register, there must be ________. (a) one clock pulse (b) four clock pulses (c) eight clock pulses (d) one clock pulse for each 1 in the data
    Tags: clock, shift, registers, data, pulses, exercise, nibble, register, electronics, engineering
  • Shift Registers - 17Shift Registers » Exercise - 117. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________. (a) 1110 (b) 0111 (c) 1000 (d) 1001
    Tags: shift, register, nibble, registers, pulses, clock, serial, waiting, bit, exercise
  • Shift Registers - 18Shift Registers » Exercise - 118. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________. (a) 1110 (b) 0001 (c) 1100 (d) 1000
    Tags: shift, registers, exercise, in/parallel, register, clock, pulses, data, electronics, engineering
  • Shift Registers - 22Shift Registers » Exercise - 122. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________. (a) 16 s (b) 8 s (c) 4 s (d) 2 s
    Tags: shift, registers, exercise, bit, serial, register, clock, electronics, engineering
  • Shift Registers - 43Shift Registers » Exercise - 143. What is meant by parallel load of a shift register? (a) All FFs are preset with data. (b) Each FF is loaded with data, one (c) (d)
    Tags: shift, registers, data, exercise, register, electronics, engineering

LEAVE A REPLY

Please enter your comment!
Please enter your name here