Shift Registers » Exercise - 140. When an 8-bit serial in/serial out shift register is used for a 20 s time delay, the clock frequency is ________. (a) 40 kHz (b) 50 kHz (c) 400 kHz (d) 500 kHz
Shift Registers » Exercise - 141. An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output? (a) 1.67 s (b) 26.67 s (c) 26.7 ms (d) 267 ms
Shift Registers » Exercise - 118. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________. (a) 1110 (b) 0001 (c) 1100 (d) 1000
Shift Registers » Exercise - 130. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________. (a) 0000 (b) 1111 (c) 0111 (d) 1000
Shift Registers » Exercise - 126. Which is not characteristic of a shift register? (a) Serial in/parallel in (b) Serial in/parallel out (c) Parallel in/serial out (d) Parallel in/parallel out