36. Assume a 4-bit parallel in/serial out shift register is loaded with a binary number. How many clock pulses are required after the parallel load has occurred before the first bit in the sequence appears on the serial output line?
(a) 0 (b) 1 (c) 2 (d) 3
Answer
Answer : (b)
Explanation
Explanation : No answer description available for this question. Let us discuss.
Shift Registers » Exercise - 128. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains ________. (a) 10111000 (b) 10110111 (c) 11110000 (d) 11111100
Shift Registers » Exercise - 114. The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses? (a) 0000 (b) 0010 (c) 1000 (d) 1111
Shift Registers » Exercise - 137. A type of shift register in which the Q or Q output of one stage is not connected to the input of the next stage is ________. (a) parallel in/serial out (b) serial in/parallel out (c) serial in/serial out (d) parallel in/parallel out