31. The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses?
(a) 10011100
(b) 11000000
(c) 00001100
(d) 11110000
32. With a 50 kHz clock frequency, six bits can be serially entered into a shift register in ________.
(a) 12 s
(b) 120 s
(c) 12 ms
(d) 120 ms
33. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________.
(a) 4 μs
(b) 40 μs
(c) 400 μs
(d) 40 ms
34. Assume a LOW logic level is placed on the SHIFT/LOAD input of a 74195 shift register. The output will change ________.
(a) immediately
(b) if the CLOCK is also LOW
(c) on the next clock leading edge
(d) depending on the J and K inputs
35. A type of shift register that requires access to the Q outputs of all stages is ________.
(a) parallel in/serial out
(b) serial in/parallel out
(c) serial in/serial out
(d) a bidirectional shift register
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