88. A positive edge-triggered D flip-flop will store a 1 when ________.
(a) the D input is HIGH and the clock transitions from HIGH to LOW (b) the D input is HIGH and the clock transitions from LOW to HIGH (c) the D input is HIGH and the clock is LOW (d) the D input is HIGH and the clock is HIGH
Answer
Answer : (b)
Explanation
Explanation : No answer description available for this question. Let us discuss.
555555555553. For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the input is HIGH. What is the status of the outputs? (a) All are HIGH. (b) All are LOW. (c) All but are LOW. (d) All but are HIGH.
555555555530. For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be HIGH. What is the status of the Y output? (a) LOW (b) HIGH (c) Don't Care (d) Cannot be determined
555555555511. The output of an AND gate is LOW ________. (a) all the time (b) when any input is LOW (c) when any input is HIGH (d) when all inputs are HIGH