5555555555
63. What does the triangle on the clock input of a J-K flip-flop mean?
(a) level enabled
(b) edg
(c)
(d)
Explanation
Explanation : No answer description available for this question. Let us discuss.
Subject Name : Electronics Engineering |
Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT
|
Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
Electronics & Communication Engineering Books
|
Related Posts
555555555568. When is a flip-flop said to be transparent? (a) when the Q output is opposite the input (b) when the Q output follows the input (c) (d) Tags: input, flip, flops, flip-flop, electronics, engineering
555555555550. How many flip-flops are in the 7475 IC? (a) 1 (b) 2 (c) 4 (d) 8 Tags: flip, flops, electronics, engineering
555555555589. A J-K flip-flop is in a "no change" condition when ________. (a) J = 1, K = 1 (b) J = 1, K = 0 (c) J = 0, K = 1 (d) J = 0, K = 0 Tags: flip, flops, j-k, flip-flop, electronics, engineering
555555555549. How is a J-K flip-flop made to toggle? (a) J = 0, K = 0 (b) J = 1, K = 0 (c) J = 0, K = 1 (d) J = 1, K = 1 Tags: flip, flops, j-k, flip-flop, electronics, engineering
555555555560. On a J-K flip-flop, when is the flip-flop in a hold condition? (a) J = 0, K = 0 (b) J = 1, K = 0 (c) J = 0, K = 1 (d) J = 1, K = 1 Tags: flip-flop, flip, flops, j-k, electronics, engineering