56. To completely load and then unload an 8-bit register requires how many clock pulses?
(a) 2
(b) 4
(c) 8
(d) 16
57. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
(a) clock is LOW
(b) slave is transferring
(c) flip-flop is reset
(d) clock is HIGH
58. The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.
(a) opposite, active clock edge
(b) inverted, positive clock edge
(c) quiescent, negative clock edge
(d) reset, synchronous clock edge
59. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.
(a) parity error checking
(b) ones catching
(c) digital discrimination
(d) digital filtering
60. On a J-K flip-flop, when is the flip-flop in a hold condition?
(a) J = 0, K = 0
(b) J = 1, K = 0
(c) J = 0, K = 1
(d) J = 1, K = 1
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