5555555555
52. Propagation delay time, tPLH, is measured from the ________.
(a) triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
(b) triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
(c) preset input to the LOW-to-HIGH transition of the output
(d) clear input to the HIGH-to-LOW transition of the output
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books
|
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
555555555572. What is the difference between the enable input of the 7475 and the clock input of the 7474? (a) The 7475 is edge-triggered. (b) (c) (d)- 5555555555154. A gated D latch does not have ________. (a) a clock input (b) an enable input (c) a output (d) steering gates
- 555555555568. When is a flip-flop said to be transparent? (a) when the Q output is opposite the input (b) when the Q output follows the input (c) (d)
- 555555555598. The output pulse width of a 555 monostable circuit with R1 = 4.7 k and C1 = 47 F is ________. (a) 24 s (b) 24 ms (c) 243 ms (d) 243 s
- 5555555555117. What is one disadvantage of an S-R flip-flop? (a) It has no enable input. (b) It has an invalid state. (c) It has no clock input. (d) It has only a single output.