5555555555
54. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
(a) 10.24 kHz
(b) 5 kHz
(c) 30.24 kHz
(d) 15 kHz
| Subject Name : Electronics Engineering |
| Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT |
| Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant |
| Electronics & Communication Engineering Books
|
| GATE 2023 Total Info | ENGG DIPLOMA | UGC NET Total Info |
| IES 2023 Total Info | PSUs 2022 Total Info | CSIR UGC NET Total Info |
| JAM 2023 Total Info | M TECH 2023 Total Info | RAILWAY 2022 Total Info |
Related Posts
Flip-Flops » Exercise - 121. How many flip-flop are needed to divide the input frequency by 64 ? (a) 2 (b) 4 (c) 6 (d) 8- 555555555592. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________. (a) 1 kHz (b) 2 kHz (c) 4 kHz (d) 16 kHz
- Counters » Exercise - 1112. ________ is the output frequency of the counter shown below. (a) 4 MHz (b) 20 kHz (c) 210.5 kHz (d) 800 Hz
- Counters » Exercise - 152. A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input clock frequency is 60 MHz. (a) 500 kHz (b) 1,500 kHz (c) 6 MHz (d) 5 MHz
- Counters » Exercise - 1123. A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________. (a) 1.25 kHz (b) 2.50 kHz (c) 160 kHz (d) 320 kHz