36. Assume a 4-bit parallel in/serial out shift register is loaded with a binary number. How many clock pulses are required after the parallel load has occurred before the first bit in the sequence appears on the serial output line?
(a) 0
(b) 1
(c) 2
(d) 3
37. A type of shift register in which the Q or Q output of one stage is not connected to the input of the next stage is ________.
(a) parallel in/serial out
(b) serial in/parallel out
(c) serial in/serial out
(d) parallel in/parallel out
38. A Johnson counter, constructed with N flip-flops, has how many unique states?
(a) N
(b) 2N
(c) 2N
(d) N2
39. An 8-bit serial in/parallel out shift register is clocked at 4 MHz and is used to delay a serial digital signal by 1.25 s. The output that has the proper delay is ________.
(a) QE
(b) QF
(c) QG
(d) QH
40. When an 8-bit serial in/serial out shift register is used for a 20 s time delay, the clock frequency is ________.
(a) 40 kHz
(b) 50 kHz
(c) 400 kHz
(d) 500 kHz
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