Shift Registers – 39

Shift Registers » Exercise – 1

39. An 8-bit serial in/parallel out shift register is clocked at 4 MHz and is used to delay a serial digital signal by 1.25 s. The output that has the proper delay is ________.

(a) QE
(b) QF
(c) QG
(d) QH

Answer
Answer : (a)
Explanation
Explanation : No answer description available for this question. Let us discuss.
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