26. Which is not characteristic of a shift register?
(a) Serial in/parallel in
(b) Serial in/parallel out
(c) Parallel in/serial out
(d) Parallel in/parallel out
27. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?
(a) 1101000000
(b) 0011010000
(c) 1100000000
(d) 0000000000
28. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains ________.
(a) 10111000
(b) 10110111
(c) 11110000
(d) 11111100
29. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________.
(a) 01110
(b) 00001
(c) 00101
(d) 00110
30. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________.
(a) 0000
(b) 1111
(c) 0111
(d) 1000
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