126. A gated S-R latch and its associated waveforms are shown below. What, if anything, is wrong and what could be causing the problem?
(a) The output is always low; the circuit is defective.
(b) The Q output should be the complement of the output; the S and R terminals are reversed.
(c) The Q should be following the R input; the R input is defective.
(d) There is nothing wrong with the circuit.
127. A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?
(a) The PRESET and CLEAR terminals may have been left floating; they should be properly terminated if not being used.
(b) The problem is caused by a race condition between the J and K inputs; an inverter should be inserted in one of the terminals to correct the problem.
(c) A race condition exists between the Q and Q outputs to the AND gate; the AND gate should be replaced with a NAND gate.
(d) A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop.
128. The circuit given below fails to function; the inputs are checked with a logic probe and the following indications are obtained: CLK, J1, J2, J3, K1, K2, and K3 are pulsing. Q and are HIGH. and PRE are LOW. What could be causing the problem?
(a) There is no problem.
(b) The clock should be held HIGH.
(c) The PRE is stuck LOW.
(d) The CLR is stuck HIGH.
129. Which is not an Altera primitive port identifier?
(a) clk
(b) ena
(c) clr
(d) prn
130. In VHDL, how many inputs will a primitive JK flip-flop have?
(a) 2
(b) 3
(c) 4
(d) 5
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