146. The signal used to identify edge-triggered flip-flops is ________.
(a) a bubble on the clock input
(b) an inverted “L” on the output
(c) the letter “E” on the enable input
(d) a triangle on the clock input
147. When the output of the NOR gate S-R flip-flop is Q = 0 and , the inputs are:
(a) S = 1, R = 1
(b) S = 1, R = 0
(c) S = 0, R = 1
(d) S = 0, R = 0
148. The term hold always means ________.
(a)
(b)
(c)
(d) no change
149. A gated S-R flip-flop is in the hold condition whenever ________.
(a) the Gate Enable is HIGH
(b) the Gate Enable is LOW
(c) the S and R inputs are both LOW
(d) the Gate Enable is HIGH and the S and R inputs are both LOW
150. A gated S-R flip-flop goes into the CLEAR condition when ________.
(a) S is HIGH; R is LOW; EN is HIGH
(b) S is LOW; R is HIGH; EN is HIGH
(c) S is LOW; R is HIGH; EN is LOW
(d) S is HIGH; R is LOW; EN is LOW
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- 555555555571. Which of the following describes the operation of a positive edge-triggered D flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
- 5555555555113. If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH? (a) An invalid state will exist. (b) No change will occur in the output. (c) The output will toggle. (d) The output will reset.
- 555555555574. If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high? (a) No change will occur in the output. (b) An invalid state will exist. (c) The output will toggle. (d) The output will reset.