116. As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:
(a) very long.
(b) very short.
(c) at a maximum value to enable the input control signals to stabilize.
(d) of no consequence as long as the levels are within the determinate range of value.
117. What is one disadvantage of an S-R flip-flop?
(a) It has no enable input.
(b) It has an invalid state.
(c) It has no clock input.
(d) It has only a single output.
118. An active-HIGH input S-R latch has a 1 on the S input and a 0 on the R input. What state is the latch in?
(a)
(b)
(c)
(d)
119. A 555 timer is connected for astable operation as shown below along with the output waveform. It is determined that the duty cycle should be 0.5. What steps need to be taken to correct the duty cycle, while maintaining the same output frequency?
(a) Increase the value of C.
(b) Increase Vcc and decrease RL.
(c) Decrease R1 and R2.
(d) Decrease R1 and increase R2.
120. Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as shown below. Determine if the circuit is functioning properly, and if not, what might be wrong.
(a) The circuit is functioning properly.
(b) Q2 is incorrect; the flip-flop is probably bad.
(c) The input to flip-flop 3 (D2) is probably wrong; check the source of D2.
(d) A bad connection probably exists between FF-3 and FF-4, causing FF-3 not to reset.
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51. How many flip-flops are required to produce a divide-by-128 device? (a) 1 (b) 4 (c) 6 (d) 7 52. Propagation delay time, tPLH, is measured from the ________. (a) triggering edge of the clock pulse to the LOW-to-HIGH transition of the output (b) triggering edge of the clock pulse to the HIGH-to-LOW transition of the output (c) preset input to the LOW-to-HIGH transition of the output (d) clear input to the HIGH-to-LOW transition of the output 53. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop? (a) The logic level at the D input is transferred to Q on NGT of CLK. (b) The Q output is ALWAYS identical to the CLK input if the D input is HIGH. (c) The Q output is ALWAYS identical to the D input when CLK = PGT. (d) The Q output is ALWAYS identical to the D input. 54. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz. (a) 10.24 kHz (b) 5 kHz (c) 30.24 kHz (d) 15 kHz 55. What is the difference between the 7476 and the 74LS76? (a) the 7476 is master-slave, the 74LS76…- 5555555555 40. Which of the following describes the operation of a positive edge-triggered D-type flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
- 555555555571. Which of the following describes the operation of a positive edge-triggered D flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
- 5555555555113. If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH? (a) An invalid state will exist. (b) No change will occur in the output. (c) The output will toggle. (d) The output will reset.
- 555555555574. If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high? (a) No change will occur in the output. (b) An invalid state will exist. (c) The output will toggle. (d) The output will reset.