141. A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.
(a) 3
(b) 7
(c) 10
(d) 13
142. An astable multivibrator is a circuit that ________.
(a) has two stable states
(b) is free-running
(c) produces a continuous output signal
(d) is free-running and produces a continuous output signal
143. Setup time specifies ________.
(a) the minimum time for the control levels to be maintained on the inputs prior to the triggering edge of the clock in order for data to be reliably clocked into the FF
(b) the maximum time interval required for the control levels to remain on the inputs before the triggering edge of the clock in order for the data to be reliably clocked out of the FF
(c) how long the operator has in order to get the flip-flop running before the maximum power level is exceeded
(d) how long it takes the output to change states after the clock has transitioned
144. When both inputs of a J-K pulse-triggered FF are high and the clock cycles, the output will ________.
(a) be invalid
(b) not change
(c) remain unchanged
(d) toggle
145. The advantage of a J-K flip-flop over an S-R FF is that ________.
(a) it has fewer gates
(b) it has only one output
(c) it has no invalid states
(d) it does not require a clock input
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51. How many flip-flops are required to produce a divide-by-128 device? (a) 1 (b) 4 (c) 6 (d) 7 52. Propagation delay time, tPLH, is measured from the ________. (a) triggering edge of the clock pulse to the LOW-to-HIGH transition of the output (b) triggering edge of the clock pulse to the HIGH-to-LOW transition of the output (c) preset input to the LOW-to-HIGH transition of the output (d) clear input to the HIGH-to-LOW transition of the output 53. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop? (a) The logic level at the D input is transferred to Q on NGT of CLK. (b) The Q output is ALWAYS identical to the CLK input if the D input is HIGH. (c) The Q output is ALWAYS identical to the D input when CLK = PGT. (d) The Q output is ALWAYS identical to the D input. 54. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz. (a) 10.24 kHz (b) 5 kHz (c) 30.24 kHz (d) 15 kHz 55. What is the difference between the 7476 and the 74LS76? (a) the 7476 is master-slave, the 74LS76…- 5555555555 40. Which of the following describes the operation of a positive edge-triggered D-type flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
- 555555555571. Which of the following describes the operation of a positive edge-triggered D flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
- 5555555555113. If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH? (a) An invalid state will exist. (b) No change will occur in the output. (c) The output will toggle. (d) The output will reset.
- 555555555574. If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high? (a) No change will occur in the output. (b) An invalid state will exist. (c) The output will toggle. (d) The output will reset.