121. In VHDL, in which declaration section is a COMPONENT declared?
(a) Architecture
(b) Library
(c) Entity
(d) Port map
122. Which of the following best describes the action of pulse-triggered FF’s?
(a) The clock and the S-R inputs must be pulse shaped.
(b) The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
(c) A pulse on the clock transfers data from input to output.
(d) The synchronous inputs must be pulsed.
123. What is another name for a one-shot?
(a) Monostable
(b) Multivibrator
(c) Bistable
(d) Astable
124. Which of the following is not generally associated with flip-flops?
(a) Hold time
(b) Propagation delay time
(c) Interval time
(d) Set up time
125. A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?
(a) The power supply is probably noisy.
(b) The switch contacts are bouncing.
(c) The socket contacts on the register IC are corroded.
(d) The register IC is intermittent and failure is imminent.
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51. How many flip-flops are required to produce a divide-by-128 device? (a) 1 (b) 4 (c) 6 (d) 7 52. Propagation delay time, tPLH, is measured from the ________. (a) triggering edge of the clock pulse to the LOW-to-HIGH transition of the output (b) triggering edge of the clock pulse to the HIGH-to-LOW transition of the output (c) preset input to the LOW-to-HIGH transition of the output (d) clear input to the HIGH-to-LOW transition of the output 53. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop? (a) The logic level at the D input is transferred to Q on NGT of CLK. (b) The Q output is ALWAYS identical to the CLK input if the D input is HIGH. (c) The Q output is ALWAYS identical to the D input when CLK = PGT. (d) The Q output is ALWAYS identical to the D input. 54. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz. (a) 10.24 kHz (b) 5 kHz (c) 30.24 kHz (d) 15 kHz 55. What is the difference between the 7476 and the 74LS76? (a) the 7476 is master-slave, the 74LS76…- 5555555555 40. Which of the following describes the operation of a positive edge-triggered D-type flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
- 555555555571. Which of the following describes the operation of a positive edge-triggered D flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
- 5555555555113. If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH? (a) An invalid state will exist. (b) No change will occur in the output. (c) The output will toggle. (d) The output will reset.
- 555555555574. If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high? (a) No change will occur in the output. (b) An invalid state will exist. (c) The output will toggle. (d) The output will reset.