Counters » Exercise – 2
51. Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
(a) input clock pulses are applied only to the first and last stages.
(b) input clock pulses are applied only to the last stage.
(c) input clock pulses are applied simultaneously to each stage.
(d) input clock pulses are not used to activate any of the counter stages.
52. A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input clock frequency is 60 MHz.
(a) 500 kHz
(b) 1,500 kHz
(c) 6 MHz
(d) 5 MHz
53. How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?
(a) 128 gates, 6 inputs to each gate
(b) 64 gates, 5 inputs to each gate
(c) 64 gates, 6 inputs to each gate
(d) 128 gates, 5 inputs to each gate
54. To operate correctly, starting a ring counter requires:
(a) clearing one flip-flop and presetting all the others.
(b) clearing all the flip-flops.
(c) presetting one flip-flop and clearing all the others.
(d) presetting all the flip-flops.
55. How many flip-flops are required to construct a decade counter?
- Counters » Exercise - 3 101. The counter circuit and associated waveforms shown below are for a(n) ________ counter, and the correct output waveform for QB is shown by waveform ________. (a) synchronous, a (b) asynchronous, b (c) synchronous, c (d) asynchronous, d 102. The given circuit is a(n) ________. (a) three-bit synchronous binary counter (b) eight-bit asynchronous binary flip-flop (c) two-bit asynchronous binary counter (d) four-bit asynchronous binary counter 103. Asynchronous counters are often called ________ counters. (a) toggle (b) ripple (c) binary (d) flip-flop 104. The given circuit represents a(n) ________. (a) four-bit binary counter (b) asynchronous BCD decade counter (c) synchronous BCD decade counter (d) BCD-to-decimal decoder 105. A BCD counter has ________ states. (a) 8 (b) 9 (c) 10 (d) 11 106. A sequential circuit design is used to ________. (a) count up (b) count down (c) decode an end count (d) count in a random order 107. The circuit shown below is a ________. (a) parallel in/serial out register (b) serial in/parallel load register (c) multiplexer (d) demultiplexer 108. In order to use a shift register as a counter, ________. (a) the register's serial input is the counter input and the serial output is the counter…
- 151. The following waveform pattern is for a(n) ________. (a) 2-input AND gate (b) 2-input OR gate (c) Exclusive-OR gate (d) None of the above 152. The following waveform pattern is for a(n) ________. (a) 2-input AND gate (b) 2-input OR gate (c) Exclusive-OR gate (d) None of the above 153. The symbol shown represents a(n) ________. (a) AND gate (b) OR gate (c) NAND gate (d) NOR gate 154. The symbol shown represents ________. (a) AND-OR logic (b) AOI logic (c) XOR gate (d) XNOR gate 155. The expression can be directly implemented using only ________. (a) an XOR gate (b) an XNOR gate (c) an AOI circuit (d) three 2-input NAND gates 156. Assume you have A, B, C, and D available but not their complements. The minimum number of 2-input NAND gates required to implement the equation is ________. (a) 3 (b) 4 (c) 5 (d) 6 157. A gate can drive a number of load gate inputs up to its specified ________. (a) supply voltage (b) noise margin (c) fan-in (d) fan-out 158. If both inputs of a 2-input NOR gate are connected, the gate will function as an ________. (a) OR gate (b) AND gate…
- 251. The inputs/outputs of an analog multiplexer/demultiplexer are: (a) bidirectional (b) unidirectional (c) even parity (d) binary-coded decimal 252. Most demultiplexers facilitate which type of conversion? (a) decimal-to-hexadecimal (b) single input, multiple outputs (c) ac to dc (d) odd parity to even parity 253. What is the function of an enable input on a multiplexer chip? (a) to apply Vcc (b) to connect ground (c) to active the entire chip (d) to active one half of the chip 254. What is the status of the inputs S0, S1, and S2 of the 74151 eight-line multiplexer in order for the output Y to be a copy of input I5? (a) S0 = 0, S1 = 1, S2 = 0 (b) S0 = 0, S1 = 0, S2 = 1 (c) S0 = 1, S1 = 1, S2 = 0 (d) S0 = 1, S1 = 0, S2 = 1 255. One multiplexer can take the place of: (a) several SSI logic gates (b) combinational logic circuits (c) several Ex-NOR gates (d) several SSI logic gates or combinational logic circuits 256. How many select lines would be required for an 8-line-to-1-line multiplexer? (a) 2 (b) 3 (c) 4 (d) 8 257. One…