# Counters – Exercise – 2

Exercise – 2

51. Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:

(a) input clock pulses are applied only to the first and last stages.
(b) input clock pulses are applied only to the last stage.
(c) input clock pulses are applied simultaneously to each stage.
(d) input clock pulses are not used to activate any of the counter stages.

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52. A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input clock frequency is 60 MHz.

(a) 500 kHz
(b) 1,500 kHz
(c) 6 MHz
(d) 5 MHz

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53. How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?

(a) 128 gates, 6 inputs to each gate
(b) 64 gates, 5 inputs to each gate
(c) 64 gates, 6 inputs to each gate
(d) 128 gates, 5 inputs to each gate

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54. To operate correctly, starting a ring counter requires:

(a) clearing one flip-flop and presetting all the others.
(b) clearing all the flip-flops.
(c) presetting one flip-flop and clearing all the others.
(d) presetting all the flip-flops.

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55. How many flip-flops are required to construct a decade counter?

(a) 10
(b) 8
(c) 5
(d) 4

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