Counters – Exercise – 2

86. The process of designing a synchronous counter that will count in a nonbinary manner is primarily based on:

(a) external logic circuits that decode the various states of the counter to apply the correct logic levels to the J-K inputs
(b) modifying BCD counters to change states on every second input clock pulse
(c) modifying asynchronous counters to change states on every second input clock pulse
(d) elimination of the counter stages and the addition of combinational logic circuits to produce the desired counts

87. How many natural states will there be in a 4-bit ripple counter?

(a) 4
(b) 8
(c) 16
(d) 32

88. What is the difference between combinational logic and sequential logic?

(a) Combinational circuits are not triggered by timing pulses, sequential circuits are triggered by timing pulses.
(b) Combinational and sequential circuits are both triggered by timing pulses.
(c)
(d)

89. Synchronous counters eliminate the delay problems encountered with asynchronous counters because the:

(a) input clock pulses are applied only to the first and last stages
(b) input clock pulses are applied only to the last stage
(c) input clock pulses are not used to activate any of the counter stages
(d) input clock pulses are applied simultaneously to each stage

90. A MOD-16 synchronous counter has inputs labeled . These inputs would most probably be used to:

(a) reset the counter to 0000 at the end of each count cycle
(b) preset the counter to a value determined by the inputs any time the is active-HIGH
(c) preset the counter to a value determined by the inputs any time the is active-LOW
(d) reset the counter to 0000 any time is active-HIGH and is active-LOW

Related Posts