Counters – 51

Counters » Exercise – 1

51. Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:

(a) input clock pulses are applied only to the first and last stages.
(b) input clock pulses are applied only to the last stage.
(c) input clock pulses are applied simultaneously to each stage.
(d) input clock pulses are not used to activate any of the counter stages.

Answer
Answer : (c)
Explanation
Explanation : No answer description available for this question. Let us discuss.
Subject Name : Electronics Engineering
Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT
Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant
Electronics & Communication Engineering Books

Sale
Question Bank On Electronics & Communication Engineering
Book - question bank on electronics & communication engineering; Language: english; Binding: paperback
₹ 317
Sale
A Handbook for Electronics Engineering(Old Edition)
Made Easy Editorial Board (Author); Marathi (Publication Language); 620 Pages - 01/01/2015 (Publication Date) - Made Easy Publications (Publisher)
₹ 320
Basic Electronic Devices and Circuits
Patil (Author); English (Publication Language)
Electronic Circuits: Analysis and Design (SIE) | 3rd Edition
Neamen, Donald (Author); English (Publication Language); 1351 Pages - 08/25/2006 (Publication Date) - McGraw Hill Education (Publisher)
₹ 1,290

GATE 2023 Total InfoENGG DIPLOMAUGC NET Total Info
IES 2023 Total InfoPSUs 2022 Total InfoCSIR UGC NET Total Info
JAM 2023 Total InfoM TECH 2023 Total InfoRAILWAY 2022 Total Info

Related Posts

  • Counters - 89Counters » Exercise - 189. Synchronous counters eliminate the delay problems encountered with asynchronous counters because the: (a) input clock pulses are applied only to the first and last stages (b) input clock pulses are applied only to the last stage (c) input clock pulses are not used to activate any of the counter stages (d) input clock pulses are applied simultaneously to each stage
    Tags: counters, input, pulses, clock, applied, stages, stage, delay, problems, encountered
  • Counters - 117Counters » Exercise - 1117. Many parallel counters use ________ presetting whereby the counter is preset on the active transition of the same clock signal that is used for counting. (a) feedback (b) synchronous (c) ripple (d) asynchronous
    Tags: counters, exercise, parallel, counter, clock, synchronous, ripple, asynchronous, electronics, engineering
  • Counters - 8Counters » Exercise - 1 8. It is a counter where the flip-flops do not change states at exactly the same time, as they do not have a common clock pulse. (a) Asynchronous Ripple Counter (b) Synchronous Ripple Counter (c) Counter (d) All of the above
    Tags: counter, counters, ripple, exercise, clock, asynchronous, synchronous, electronics, engineering
  • Counters - 95Counters » Exercise - 195. For a multistage counter to be truly synchronous, the ________ of each stage must be connected to ________. (a) Cp, the same clock input line (b) CE, the same clock input line (c) , the terminal count output (d) , both clock input lines
    Tags: clock, input, counters, exercise, counter, synchronous, stage, electronics, engineering
  • Counters - 35Counters » Exercise - 135. The final output of a modulus-8 counter occurs one time for every ________. (a) 8 clock pulses (b) 16 clock pulses (c) 24 clock pulses (d) 32 clock pulses
    Tags: clock, pulses, counters, exercise, counter, electronics, engineering

LEAVE A REPLY

Please enter your comment!
Please enter your name here