91. The process or sequence of all operations carried out to ultimately program a target device is called the ________.
(a) graphic entry
(b) LAB
(c) downloading
(d) design flow
92. A GAL22V10 ________.
(a) has up to 32 inputs and 10 outputs
(b) is a type of SPLD
(c) has 10 inputs and 22 outputs
(d) is downloadable from the manufacturer’s Web site
93. A method for the automated testing of printed circuit boards is called a(n) ________.
(a) bed-of-nails
(b) LUT
(c) CLB
(d) CPLD
94. FLEX10K devices are generally classified as ________.
(a) PLDs
(b) FPGAs
(c) HCPLDs
(d) CPLDs
95. The MAX+PLUS II compiler will automatically program a macrocell to borrow up to ________ product terms from each of the 3 adjacent macrocells in the same LAB.
(a) 4
(b) 5
(c) 6
(d) 7
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101. All inputs to the MAX7000S device and all macrocell outputs feed the ________. (a) LUT (b) PIA (c) LAB (d) PIA and LAB 102. The major structures in the MAX7000S are the ________ and ________. (a) LUT, PIA (b) FMUX, LAB (c) LAB, PIA (d) LUT, FMUX 103. In the GAL16V8, the ________ selects the signal that is fed back into the input matrix. (a) FMUX (b) OMUX (c) PTMUX (d) TSMUX 104. In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________. (a) asynchronous reset, synchronous preset (b) asynchronous preset, synchronous reset (c) asynchronous clear, synchronous set (d) asynchronous set, synchronous clear 105. In the MAX7000S device up to ________ signals can feed each LAB from the PIA. (a) 0 (b) 18 (c) 36 (d) 72 106. Design costs for standard cell ASICs are ________ those for MPGAs. (a) lower than (b) about the same as (c) higher than (d) none of the above 107. Gated arrays are ________ circuits that offer hundreds of thousands of gates. (a) VLSI (b) full custom (c) LSI (d) ULSI 108. Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions. (a) AND array…- Home » Electronics Engineering » Digital Electronics » Logic Families
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