96. In a MAX7000S device, when an I/O pin is configured as an input, the associated macrocell can be used for ________.
(a) buried logic
(b) another output
(c) extra speed
(d) in-system testing
97. The flexibility of the GAL16V8 is in its ________.
(a) AND/OR array
(b) D flip-flops
(c) programmable output logic macro cells
(d) EEPROM
98. The EPM 798S is a(n) ________ device.
(a) PLD
(b) JTAG
(c) EEPROM
(d) ISP
99. In the GAL16V8, the ________ controls the tristate buffer’s enable input.
(a) FMUX
(b) OMUX
(c) PTMUX
(d) TMUX
100. The field programmable logic array was the first ________ programmable logic device.
(a) understandable
(b) logic array
(c) multifunction
(d) nonmemory
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101. All inputs to the MAX7000S device and all macrocell outputs feed the ________. (a) LUT (b) PIA (c) LAB (d) PIA and LAB 102. The major structures in the MAX7000S are the ________ and ________. (a) LUT, PIA (b) FMUX, LAB (c) LAB, PIA (d) LUT, FMUX 103. In the GAL16V8, the ________ selects the signal that is fed back into the input matrix. (a) FMUX (b) OMUX (c) PTMUX (d) TSMUX 104. In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________. (a) asynchronous reset, synchronous preset (b) asynchronous preset, synchronous reset (c) asynchronous clear, synchronous set (d) asynchronous set, synchronous clear 105. In the MAX7000S device up to ________ signals can feed each LAB from the PIA. (a) 0 (b) 18 (c) 36 (d) 72 106. Design costs for standard cell ASICs are ________ those for MPGAs. (a) lower than (b) about the same as (c) higher than (d) none of the above 107. Gated arrays are ________ circuits that offer hundreds of thousands of gates. (a) VLSI (b) full custom (c) LSI (d) ULSI 108. Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions. (a) AND array…- Home » Electronics Engineering » Digital Electronics » Logic Families
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