51. An Altera FLEX10K device uses a(n) ________ architecture.
(a) OR array
(b) AND array
(c) OR and AND array
(d) look-up table
52. In a FLEX10K device, the carry chain provides a fast carry forward function between ________.
53. The GAL16V8 has architecture that is very similar to the ________ device.
54. An EPM 7128S in a ________ PQFP package has 12 I/O per LAB plus 4 additional input-only pins for a total of 100 pins.
55. Four subcategories of ASIC devices are available to create digital systems. These are PLDs, gate arrays, standard cells, and ________.
(b) full custom
- 101. All inputs to the MAX7000S device and all macrocell outputs feed the ________. (a) LUT (b) PIA (c) LAB (d) PIA and LAB 102. The major structures in the MAX7000S are the ________ and ________. (a) LUT, PIA (b) FMUX, LAB (c) LAB, PIA (d) LUT, FMUX 103. In the GAL16V8, the ________ selects the signal that is fed back into the input matrix. (a) FMUX (b) OMUX (c) PTMUX (d) TSMUX 104. In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________. (a) asynchronous reset, synchronous preset (b) asynchronous preset, synchronous reset (c) asynchronous clear, synchronous set (d) asynchronous set, synchronous clear 105. In the MAX7000S device up to ________ signals can feed each LAB from the PIA. (a) 0 (b) 18 (c) 36 (d) 72 106. Design costs for standard cell ASICs are ________ those for MPGAs. (a) lower than (b) about the same as (c) higher than (d) none of the above 107. Gated arrays are ________ circuits that offer hundreds of thousands of gates. (a) VLSI (b) full custom (c) LSI (d) ULSI 108. Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions. (a) AND array…