86. A complex programmable logic device that consists of multiple SPLD arrays with programmable interconnections is called a ________.
(a) bed-of-nails
(b) boundary scan
(c) CLB
(d) CPLD
87. An application program in the development software package that controls the operation of the software is called a ________.
(a) compiler
(b) bed-of-nails
(c) boundary scan
(d) primitive
88. The final step in a design flow in which the logic design is implemented in the target device is called ________.
(a) design entry
(b) simulation
(c) downloading
(d) compiling
89. The Boolean expression AB + CD is an example of ________.
(a) PAL
(b) GAL
(c) SOP
(d) POS
90. A macrocell is ________.
(a) part of a PAL or GAL
(b) a type of one-time programmable SPLD
(c) an example of intellectual property
(d) a logic array block
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101. All inputs to the MAX7000S device and all macrocell outputs feed the ________. (a) LUT (b) PIA (c) LAB (d) PIA and LAB 102. The major structures in the MAX7000S are the ________ and ________. (a) LUT, PIA (b) FMUX, LAB (c) LAB, PIA (d) LUT, FMUX 103. In the GAL16V8, the ________ selects the signal that is fed back into the input matrix. (a) FMUX (b) OMUX (c) PTMUX (d) TSMUX 104. In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________. (a) asynchronous reset, synchronous preset (b) asynchronous preset, synchronous reset (c) asynchronous clear, synchronous set (d) asynchronous set, synchronous clear 105. In the MAX7000S device up to ________ signals can feed each LAB from the PIA. (a) 0 (b) 18 (c) 36 (d) 72 106. Design costs for standard cell ASICs are ________ those for MPGAs. (a) lower than (b) about the same as (c) higher than (d) none of the above 107. Gated arrays are ________ circuits that offer hundreds of thousands of gates. (a) VLSI (b) full custom (c) LSI (d) ULSI 108. Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions. (a) AND array…- Home » Electronics Engineering » Digital Electronics » Logic Families
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