71. Which is not a type of PLD?
(a) SPLD
(b) HPLD
(c) CPLD
(d) FPGA
72. What is PROM?
(a) SPLD
(b) QPLD
(c) HPLD
(d) PLD
73. What does a dot mean when placed on a PLD circuit diagram?
(a) A point that is programmable
(b) A point that cannot change
(c) An intersection of logic blocks
(d) An input or output point
74. Which is not a part of a GAL16V8’s OLMC?
(a) TSMUX
(b) OMUX
(c) FMUX
(d) PSMUX
75. What programmable technology is used in FPGA devices?
(a) SRAM
(b) FLASH
(c) Antifuse
(d) All of the above
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101. All inputs to the MAX7000S device and all macrocell outputs feed the ________. (a) LUT (b) PIA (c) LAB (d) PIA and LAB 102. The major structures in the MAX7000S are the ________ and ________. (a) LUT, PIA (b) FMUX, LAB (c) LAB, PIA (d) LUT, FMUX 103. In the GAL16V8, the ________ selects the signal that is fed back into the input matrix. (a) FMUX (b) OMUX (c) PTMUX (d) TSMUX 104. In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________. (a) asynchronous reset, synchronous preset (b) asynchronous preset, synchronous reset (c) asynchronous clear, synchronous set (d) asynchronous set, synchronous clear 105. In the MAX7000S device up to ________ signals can feed each LAB from the PIA. (a) 0 (b) 18 (c) 36 (d) 72 106. Design costs for standard cell ASICs are ________ those for MPGAs. (a) lower than (b) about the same as (c) higher than (d) none of the above 107. Gated arrays are ________ circuits that offer hundreds of thousands of gates. (a) VLSI (b) full custom (c) LSI (d) ULSI 108. Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions. (a) AND array…- Home » Electronics Engineering » Digital Electronics » Logic Families
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