61. How many combinations are handled in an LUT?
(a) 4
(b) 8
(c) 16
(d) 32
62. What does the Altera FLEX10K PLD use in place of AND and OR arrays?
(a) Nothing, it uses AND and OR arrays.
(b) Look-up tables
(c) SRAM-based memory
(d) HPLD architecture
63. What is an EPM7128S?
(a) An Altera MAX7000S CPLD
(b) An Altera UP2
(c) A DeVry eSOC
(d) A BSR PL DT-2
64. What can the GAL22V10 do that the GAL16V8 cannot?
(a) It has an extra-large array.
(b) It is in-system programmable.
(c) It has twice the special function pins.
(d) All of the above
65. What is the input/output pin configuration of the GAL22V10?
(a) 10 output pins and 12 input pins
(b) 2 special-purpose pins
(c) 8 pins that are either inputs or outputs
(d) All of the above
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101. All inputs to the MAX7000S device and all macrocell outputs feed the ________. (a) LUT (b) PIA (c) LAB (d) PIA and LAB 102. The major structures in the MAX7000S are the ________ and ________. (a) LUT, PIA (b) FMUX, LAB (c) LAB, PIA (d) LUT, FMUX 103. In the GAL16V8, the ________ selects the signal that is fed back into the input matrix. (a) FMUX (b) OMUX (c) PTMUX (d) TSMUX 104. In a GAL16V8, the D flip-flops contained in the OLMCs have ________ and ________. (a) asynchronous reset, synchronous preset (b) asynchronous preset, synchronous reset (c) asynchronous clear, synchronous set (d) asynchronous set, synchronous clear 105. In the MAX7000S device up to ________ signals can feed each LAB from the PIA. (a) 0 (b) 18 (c) 36 (d) 72 106. Design costs for standard cell ASICs are ________ those for MPGAs. (a) lower than (b) about the same as (c) higher than (d) none of the above 107. Gated arrays are ________ circuits that offer hundreds of thousands of gates. (a) VLSI (b) full custom (c) LSI (d) ULSI 108. Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions. (a) AND array…