51. The RAM circuit given below is suspected of being bad. A check with a logic probe shows pulse activity on all of the address lines and data inputs. The / line and inputs are forced HIGH and the data output lines are checked with the logic probe. Q0, Q2, and Q3 show a dim indication on the logic probe; Q1 indicates a HIGH level on the logic probe. What, if anything, is wrong with the circuit?
(a) The Q0, Q2, and Q3 output lines are open; the chip is defective.
(b) The Q1 line appears to be shorted to Vcc; replace the chip.
(c) The outputs should be active only when the / line is held LOW, so the circuit is behaving normally considering the fact that the line is HIGH.
(d) The EN input should be forced HIGH and the outputs rechecked; if they are still giving the same indications as before, then the three outputs are definitely open and the IC will have to be replaced.
52. Which of the following faults will the checkerboard pattern test for in RAM?
(a) Short between adjacent cells
(b) Ability to store both 0s and 1s
(c) Dynamically introduced between cells
(d) All of the above
53. Nota
54. When a RAM module passes the checkerboard test it is:
(a) able to read and write only 1s.
(b) faulty.
(c) probably good.
(d) able to read and write only 0s.
55. Eight bits of digital data are normally referred to as a:
(a) group.
(b) byte.
(c) word.
(d) cell.
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