51. The RAM circuit given below is suspected of being bad. A check with a logic probe shows pulse activity on all of the address lines and data inputs. The / line and inputs are forced HIGH and the data output lines are checked with the logic probe. Q0, Q2, and Q3 show a dim indication on the logic probe; Q1 indicates a HIGH level on the logic probe. What, if anything, is wrong with the circuit?
(a) The Q0, Q2, and Q3 output lines are open; the chip is defective.
(b) The Q1 line appears to be shorted to Vcc; replace the chip.
(c) The outputs should be active only when the / line is held LOW, so the circuit is behaving normally considering the fact that the line is HIGH.
(d) The EN input should be forced HIGH and the outputs rechecked; if they are still giving the same indications as before, then the three outputs are definitely open and the IC will have to be replaced.
52. Which of the following faults will the checkerboard pattern test for in RAM?
(a) Short between adjacent cells
(b) Ability to store both 0s and 1s
(c) Dynamically introduced between cells
(d) All of the above
54. When a RAM module passes the checkerboard test it is:
(a) able to read and write only 1s.
(c) probably good.
(d) able to read and write only 0s.
55. Eight bits of digital data are normally referred to as a:
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- 101. Which type of ROM can be erased by UV light? (a) ROM (b) mask ROM (c) EPROM (d) EEPROM 102. Which type of ROM can be erased by an electrical signal? (a) ROM (b) mask ROM (c) EPROM (d) EEPROM 103. In general, the ________ have the smallest bit size and the ________ have the largest. (a) EEPROMs, Flash (b) SRAM, mask ROM (c) mask ROM, SRAM (d) DRAM, PROM 104. Which type of ROM has to be custom built by the factory? (a) ROM (b) mask ROM (c) EPROM (d) EEPROM 105. What part of a Flash memory architecture manages all chip functions? (a) I/O pins (b) floating-gate MOSFET (c) command code (d) program verify code 106. Why do most dynamic RAMs use a multiplexed address bus? (a) It is the only way to do it. (b) to make it faster (c) to keep the nu (d) 107. What is a multitap digital delay line? (a) a series of inverter gates with RC circuits between each one (b) a series of inverter gates with RL circuits between each one (c) a series of NAND gates with RC circuits between each one (d) a series of NAND gates with…