136. If data is brought into the J terminal and its complement to the K terminal, a J-K flip-flop operates as a(n) ________.
(a) S-C flip-flop
(b) D flip-flop
(c) gated S-C flip-flop
(d) TOGGLE flip-flop
137. A flip-flop operation is described as a toggle when the result after a clock is ________.
(a)
(b)
(c)
(d) change to opposite states
138. The point(s) on this timing diagram where the Q output of a D latch will be HIGH is/are ________.
(a) point 4
(b) points 3 and 4
(c) points 1 and 2
(d) points 4 and 5
139. The inputs on a 7474 D flip-flop are S, R, D, and CLK ________ is/are synchronous.
(a) Only S
(b) S and R
(c) Only D
(d) All of the above.
140. Regardless of whether you develop a description in AHDL or VHDL, the circuit’s proper operation can be verified using a ________.
(a) PROCESS
(b) computer
(c) simulator
(d) primitive library
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51. How many flip-flops are required to produce a divide-by-128 device? (a) 1 (b) 4 (c) 6 (d) 7 52. Propagation delay time, tPLH, is measured from the ________. (a) triggering edge of the clock pulse to the LOW-to-HIGH transition of the output (b) triggering edge of the clock pulse to the HIGH-to-LOW transition of the output (c) preset input to the LOW-to-HIGH transition of the output (d) clear input to the HIGH-to-LOW transition of the output 53. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop? (a) The logic level at the D input is transferred to Q on NGT of CLK. (b) The Q output is ALWAYS identical to the CLK input if the D input is HIGH. (c) The Q output is ALWAYS identical to the D input when CLK = PGT. (d) The Q output is ALWAYS identical to the D input. 54. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz. (a) 10.24 kHz (b) 5 kHz (c) 30.24 kHz (d) 15 kHz 55. What is the difference between the 7476 and the 74LS76? (a) the 7476 is master-slave, the 74LS76…- 5555555555 40. Which of the following describes the operation of a positive edge-triggered D-type flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
- 555555555571. Which of the following describes the operation of a positive edge-triggered D flip-flop? (a) If both inputs are HIGH, the output will toggle. (b) The output will follow the input on the leading edge of the clock. (c) When both inputs are LOW, an invalid state exists. (d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
- 5555555555113. If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH? (a) An invalid state will exist. (b) No change will occur in the output. (c) The output will toggle. (d) The output will reset.
- 555555555574. If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high? (a) No change will occur in the output. (b) An invalid state will exist. (c) The output will toggle. (d) The output will reset.