Shift Registers » Exercise - 114. The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses? (a) 0000 (b) 0010 (c) 1000 (d) 1111
Shift Registers » Exercise - 131. The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses? (a) 10011100 (b) 11000000 (c) 00001100 (d) 11110000
Shift Registers » Exercise - 124. To serially shift a nibble (four bits) of data into a shift register, there must be ________. (a) one clock pulse (b) four clock pulses (c) eight clock pulses (d) one clock pulse for each 1 in the data