Shift Registers – 31

Shift Registers » Exercise – 1

31. The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses?

(a) 10011100
(b) 11000000
(c) 00001100
(d) 11110000

Answer
Answer : (b)
Explanation
Explanation : No answer description available for this question. Let us discuss.
Subject Name : Electronics Engineering
Exam Name : IIT GATE, UPSC ESE, RRB, SSC, DMRC, NMRC, BSNL, DRDO, ISRO, BARC, NIELIT
Posts Name : Assistant Engineer, Management Trainee, Junior Engineer, Technical Assistant
Electronics & Communication Engineering Books

Sale
Question Bank On Electronics & Communication Engineering
Book - question bank on electronics & communication engineering; Language: english; Binding: paperback
₹ 317
Sale
A Handbook for Electronics Engineering(Old Edition)
Made Easy Editorial Board (Author); Marathi (Publication Language); 620 Pages - 01/01/2015 (Publication Date) - Made Easy Publications (Publisher)
₹ 320
Basic Electronic Devices and Circuits
Patil (Author); English (Publication Language)
Sale
Electronic Circuits: Analysis and Design (SIE) | 3rd Edition
Neamen, Donald (Author); English (Publication Language); 1351 Pages - 08/25/2006 (Publication Date) - McGraw Hill Education (Publisher)
₹ 1,200

GATE 2023 Total InfoENGG DIPLOMAUGC NET Total Info
IES 2023 Total InfoPSUs 2022 Total InfoCSIR UGC NET Total Info
JAM 2023 Total InfoM TECH 2023 Total InfoRAILWAY 2022 Total Info

Related Posts

  • Shift Registers - 14Shift Registers » Exercise - 114. The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses? (a) 0000 (b) 0010 (c) 1000 (d) 1111
    Tags: shift, bit, registers, exercise, sequence, serially, entered, right-most, parallel, register
  • Shift Registers - 28Shift Registers » Exercise - 128. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains ________. (a) 10111000 (b) 10110111 (c) 11110000 (d) 11111100
    Tags: shift, registers, register, bit, serially, right-most, parallel, exercise, clock, pulses
  • Shift Registers - 18Shift Registers » Exercise - 118. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________. (a) 1110 (b) 0001 (c) 1100 (d) 1000
    Tags: shift, registers, exercise, parallel, register, clock, pulses, outputs, electronics, engineering
  • Shift Registers - 20Shift Registers » Exercise - 120. In a 6-bit Johnson counter sequence there are a total of how many states, or bit patterns? (a) 2 (b) 6 (c) 12 (d) 24
    Tags: shift, registers, bit, exercise, sequence, electronics, engineering
  • Shift Registers - 6Shift Registers » Exercise - 1 6. A register can be either static or dynamic. (a) Shift (b) Parallel (c) Bit (d) None of the above
    Tags: shift, registers, exercise, register, parallel, bit, electronics, engineering

LEAVE A REPLY

Please enter your comment!
Please enter your name here