14. The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses?

(a) 0000 (b) 0010 (c) 1000 (d) 1111

Answer

Answer : (c)

Explanation

Explanation : No answer description available for this question. Let us discuss.

Shift Registers » Exercise - 131. The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses? (a) 10011100 (b) 11000000 (c) 00001100 (d) 11110000

Shift Registers » Exercise - 128. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains ________. (a) 10111000 (b) 10110111 (c) 11110000 (d) 11111100

Shift Registers » Exercise - 118. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________. (a) 1110 (b) 0001 (c) 1100 (d) 1000

Shift Registers » Exercise - 129. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________. (a) 01110 (b) 00001 (c) 00101 (d) 00110