Shift Registers » Exercise - 1 4. This type of register accepts inputs data simultaneously and output is also coming out parallel : (a) PIPO (b) SIPO (c) PISO (d) SISO
Shift Registers » Exercise - 132. With a 50 kHz clock frequency, six bits can be serially entered into a shift register in ________. (a) 12 s (b) 120 s (c) 12 ms (d) 120 ms
Shift Registers » Exercise - 118. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________. (a) 1110 (b) 0001 (c) 1100 (d) 1000
Shift Registers » Exercise - 168. How can parallel data be taken out of a shift register simultaneously? (a) Use the Q output of the first FF. (b) Use the Q output of the last FF. (c) Tie all of the Q outputs together. (d) Use the Q output of each FF.