Shift Registers » Exercise - 130. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________. (a) 0000 (b) 1111 (c) 0111 (d) 1000
Shift Registers » Exercise - 118. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________. (a) 1110 (b) 0001 (c) 1100 (d) 1000
Shift Registers » Exercise - 121. If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse? (a) 11101011 (b) 00010111 (c) 11110000 (d) 00000000
Shift Registers » Exercise - 127. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse? (a) 1101000000 (b) 0011010000 (c) 1100000000 (d) 0000000000