23. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
(a) 1100 (b) 0011 (c) 0000 (d) 1111
Answer
Answer : (c)
Explanation
Explanation : No answer description available for this question. Let us discuss.
Shift Registers » Exercise - 114. The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses? (a) 0000 (b) 0010 (c) 1000 (d) 1111
Shift Registers » Exercise - 131. The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses? (a) 10011100 (b) 11000000 (c) 00001100 (d) 11110000
Shift Registers » Exercise - 130. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________. (a) 0000 (b) 1111 (c) 0111 (d) 1000
Shift Registers » Exercise - 117. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________. (a) 1110 (b) 0111 (c) 1000 (d) 1001
Shift Registers » Exercise - 122. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________. (a) 16 s (b) 8 s (c) 4 s (d) 2 s