121. An open-collector output requires ________.
(a) a pull-down resistor
(b) a pull-up resistor
(c) no output resistor
(d) an output resistor
122. Which is not an output state for tristate logic?
(a) HIGH
(b) LOW
(c) High-Z
(d) Low-Z
123. TTL is alive and well, particularly in ________.
(a) industrial applications
(b) educational applications
(c) military applications
(d) commercial applications
124. Most TTL logic used today is some form of ________.
(a) Schottky TTL
(b) tristate TTL
(c) low-power TTL
(d) open-collector TTL
125. A TTL NAND gate with IIH(max) of 40 A per input drives ten TTL inputs. How much current does the drive output source?
(a) 40 A
(b) 200 A
(c) 400 A
(d) 800 A
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51. Which of the following logic families has the shortest propagation delay? (a) S-TTL (b) AS-TTL (c) HS-TTL (d) HCMOS 52. Which of the following logic families has the highest maximum clock frequency? (a) S-TTL (b) AS-TTL (c) HS-TTL (d) HCMOS 53. Which of the following will not normally be found on a data sheet? (a) Minimum HIGH level output voltage (b) Maximum LOW level output voltage (c) Minimum LOW level output voltage (d) Maximum HIGH level input current 54. Logic circuits that are designated as buffers, drivers, or buffer/drivers are designed to have: (a) a greater current/voltage capability than an ordinary logic circuit. (b) greater input current/voltage capability than an ordinary logic circuit. (c) a smaller output current/voltage capability than an ordinary logic. (d) greater input and output current/voltage capability than an ordinary logic circuit. 55. Why is the fan-out of CMOS gates frequency dependent? (a) Each CMOS input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a CMOS gate. (b) When the frequency reaches the critical value, the gate will only be capable of delivering 70% of the normal output voltage and consequently the…- 151. The following waveform pattern is for a(n) ________. (a) 2-input AND gate (b) 2-input OR gate (c) Exclusive-OR gate (d) None of the above 152. The following waveform pattern is for a(n) ________. (a) 2-input AND gate (b) 2-input OR gate (c) Exclusive-OR gate (d) None of the above 153. The symbol shown represents a(n) ________. (a) AND gate (b) OR gate (c) NAND gate (d) NOR gate 154. The symbol shown represents ________. (a) AND-OR logic (b) AOI logic (c) XOR gate (d) XNOR gate 155. The expression can be directly implemented using only ________. (a) an XOR gate (b) an XNOR gate (c) an AOI circuit (d) three 2-input NAND gates 156. Assume you have A, B, C, and D available but not their complements. The minimum number of 2-input NAND gates required to implement the equation is ________. (a) 3 (b) 4 (c) 5 (d) 6 157. A gate can drive a number of load gate inputs up to its specified ________. (a) supply voltage (b) noise margin (c) fan-in (d) fan-out 158. If both inputs of a 2-input NOR gate are connected, the gate will function as an ________. (a) OR gate (b) AND gate…
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- Logic Gates » Exercise - 2 51. Which type of gate can be used to add two bits? (a) Ex-OR (b) Ex-NOR (c) Ex-NAND (d) NOR 52. Show from the truth table how an exclusive-OR gate can be used to invert the data on one input if the other input is a special control function. (a) Using A as the control, when A = 0, X is the same as B. When A = 1, X is the same as B. (b) Using A as the control, when A = 0, X is the same as B. When A = 1, X is the inverse of B. (c) Using A as the control, when A = 0, X is the inverse of B. When A = 1, X is the same as B. (d) Using A as the control, when A = 0, X is the inverse of B. When A = 1, X is the inverse of B. 53. Parity systems are defined as either________ or ________ and will add an extra ________ to the digital information being transmitted. (a) positive, negative, byte (b) odd, even, bit (c) upper, lower, digit (d) on, off, decimal 54. The Ex-NOR is sometimes called…
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