# Logic Families – Exercise – 3

101. When the output of a standard TTL gate is HIGH, it can ________.

(a) sink 16 mA of current from the attached input gates
(b) source 400 A of current to no more than 10 attached gates
(c) source 16 mA of current to no more than 10 attached gates
(d) sink a maximum of 400 A from no more than 10 load gates

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102. Totem-pole outputs ________ be connected ________ because ________.

(a) can, in parallel, sometimes higher output current is required
(b) cannot, together, if the outputs are in opposite states excessively high currents can damage one or both of the devices
(c) should, in series, certain applications may require higher output voltage
(d) can, together, together they can handle larger load currents and higher output voltages

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103. P-MOS and N-MOS ________.

(a) represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a given gate
(b) are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC
(c) represent positive and negative MOS-type devices that can be operated from differential power supplies and are compatible with operational amplifiers
(d) None of the above are.

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104. The HIGH logic level for a standard TTL output must be at least ________.

(a) 2.4 V
(b) 2 V
(c) 0.8 V
(d) 5 V

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105. A logic probe is placed on the output of a digital circuit and the probe lamp is dimly lit. This display indicates ________.

(a) that an open or bad logic level exists
(b) a high level output
(c) a high-frequency pulse train
(d) that the supply voltage is low

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