101. How many inputs are on the logic gates of a 74HC21 IC?
102. What are the pin numbers of the outputs of the gates in a 7432 IC?
(a) 3, 6, 10, and 13
(b) 1, 4, 10, and 13
(c) 3, 6, 8, and 11
(d) 1, 4, 8, and 11
103. How many AND gates are found in a 7411 IC?
104. Which of the following equations would accurately describe a four-input OR gate when A = 1, B = 1, C = 0, and D = 0?
(a) 1 + 1 + 0 + 0 = 01
(b) 1 + 1 + 0 + 0 = 1
(c) 1 + 1 + 0 + 0 = 0
(d) 1 + 1 + 0 + 0 = 00
105. Which of the following logical operations is represented by the + sign in Boolean algebra?
- Logic Gates » Exercise - 2 51. Which type of gate can be used to add two bits? (a) Ex-OR (b) Ex-NOR (c) Ex-NAND (d) NOR 52. Show from the truth table how an exclusive-OR gate can be used to invert the data on one input if the other input is a special control function. (a) Using A as the control, when A = 0, X is the same as B. When A = 1, X is the same as B. (b) Using A as the control, when A = 0, X is the same as B. When A = 1, X is the inverse of B. (c) Using A as the control, when A = 0, X is the inverse of B. When A = 1, X is the same as B. (d) Using A as the control, when A = 0, X is the inverse of B. When A = 1, X is the inverse of B. 53. Parity systems are defined as either________ or ________ and will add an extra ________ to the digital information being transmitted. (a) positive, negative, byte (b) odd, even, bit (c) upper, lower, digit (d) on, off, decimal 54. The Ex-NOR is sometimes called…
- 151. The following waveform pattern is for a(n) ________. (a) 2-input AND gate (b) 2-input OR gate (c) Exclusive-OR gate (d) None of the above 152. The following waveform pattern is for a(n) ________. (a) 2-input AND gate (b) 2-input OR gate (c) Exclusive-OR gate (d) None of the above 153. The symbol shown represents a(n) ________. (a) AND gate (b) OR gate (c) NAND gate (d) NOR gate 154. The symbol shown represents ________. (a) AND-OR logic (b) AOI logic (c) XOR gate (d) XNOR gate 155. The expression can be directly implemented using only ________. (a) an XOR gate (b) an XNOR gate (c) an AOI circuit (d) three 2-input NAND gates 156. Assume you have A, B, C, and D available but not their complements. The minimum number of 2-input NAND gates required to implement the equation is ________. (a) 3 (b) 4 (c) 5 (d) 6 157. A gate can drive a number of load gate inputs up to its specified ________. (a) supply voltage (b) noise margin (c) fan-in (d) fan-out 158. If both inputs of a 2-input NOR gate are connected, the gate will function as an ________. (a) OR gate (b) AND gate…
- 101. When the output of a standard TTL gate is HIGH, it can ________. (a) sink 16 mA of current from the attached input gates (b) source 400 A of current to no more than 10 attached gates (c) source 16 mA of current to no more than 10 attached gates (d) sink a maximum of 400 A from no more than 10 load gates 102. Totem-pole outputs ________ be connected ________ because ________. (a) can, in parallel, sometimes higher output current is required (b) cannot, together, if the outputs are in opposite states excessively high currents can damage one or both of the devices (c) should, in series, certain applications may require higher output voltage (d) can, together, together they can handle larger load currents and higher output voltages 103. P-MOS and N-MOS ________. (a) represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a given gate (b) are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC (c) represent positive and negative MOS-type devices that can be operated from differential power supplies and are compatible with operational amplifiers (d) None of the above are. 104. The HIGH logic level for a…
- 51. The device shown here is most likely a ________. (a) comparator (b) multiplexer (c) demultiplexer (d) parity generator 52. The device shown here is most likely a ________. (a) comparator (b) multiplexer (c) demultiplexer (d) parity generator 53. For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the input is HIGH. What is the status of the outputs? (a) All are HIGH. (b) All are LOW. (c) All but are LOW. (d) All but are HIGH. 54. A circuit that can convert one of ten numerical keys pressed on a keyboard to BCD is a ________. (a) priority encoder (b) decoder (c) multiplexer (d) demultiplexer 55. What is the indication of a short on the input of a load gate? (a) Only the output of the defective gate is affected. (b) There is a signal loss to all gates on the node. (c) The affected node will be stuck in the LOW state. (d) There is a signal loss to all gates on the node, and the affected node will be stuck in the LOW state. 56. What is the indication of a short to ground in the output of a…
- 251. The inputs/outputs of an analog multiplexer/demultiplexer are: (a) bidirectional (b) unidirectional (c) even parity (d) binary-coded decimal 252. Most demultiplexers facilitate which type of conversion? (a) decimal-to-hexadecimal (b) single input, multiple outputs (c) ac to dc (d) odd parity to even parity 253. What is the function of an enable input on a multiplexer chip? (a) to apply Vcc (b) to connect ground (c) to active the entire chip (d) to active one half of the chip 254. What is the status of the inputs S0, S1, and S2 of the 74151 eight-line multiplexer in order for the output Y to be a copy of input I5? (a) S0 = 0, S1 = 1, S2 = 0 (b) S0 = 0, S1 = 0, S2 = 1 (c) S0 = 1, S1 = 1, S2 = 0 (d) S0 = 1, S1 = 0, S2 = 1 255. One multiplexer can take the place of: (a) several SSI logic gates (b) combinational logic circuits (c) several Ex-NOR gates (d) several SSI logic gates or combinational logic circuits 256. How many select lines would be required for an 8-line-to-1-line multiplexer? (a) 2 (b) 3 (c) 4 (d) 8 257. One…