51. Which of the following logic families has the shortest propagation delay?
52. Which of the following logic families has the highest maximum clock frequency?
53. Which of the following will not normally be found on a data sheet?
(a) Minimum HIGH level output voltage
(b) Maximum LOW level output voltage
(c) Minimum LOW level output voltage
(d) Maximum HIGH level input current
54. Logic circuits that are designated as buffers, drivers, or buffer/drivers are designed to have:
(a) a greater current/voltage capability than an ordinary logic circuit.
(b) greater input current/voltage capability than an ordinary logic circuit.
(c) a smaller output current/voltage capability than an ordinary logic.
(d) greater input and output current/voltage capability than an ordinary logic circuit.
55. Why is the fan-out of CMOS gates frequency dependent?
(a) Each CMOS input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a CMOS gate.
(b) When the frequency reaches the critical value, the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will be one-half of normal; this defines the upper operating frequency.
(c) The higher the number of gates attached to the output, the more frequently they will have to be serviced, thus reducing the frequency at which each will be serviced with an input signal.
(d) The input gates of the FETs are predominantly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the number of loads that may be attached to the output of the driving gate.
- 101. When the output of a standard TTL gate is HIGH, it can ________. (a) sink 16 mA of current from the attached input gates (b) source 400 A of current to no more than 10 attached gates (c) source 16 mA of current to no more than 10 attached gates (d) sink a maximum of 400 A from no more than 10 load gates 102. Totem-pole outputs ________ be connected ________ because ________. (a) can, in parallel, sometimes higher output current is required (b) cannot, together, if the outputs are in opposite states excessively high currents can damage one or both of the devices (c) should, in series, certain applications may require higher output voltage (d) can, together, together they can handle larger load currents and higher output voltages 103. P-MOS and N-MOS ________. (a) represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a given gate (b) are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC (c) represent positive and negative MOS-type devices that can be operated from differential power supplies and are compatible with operational amplifiers (d) None of the above are. 104. The HIGH logic level for a…
- Logic Gates » Exercise - 2 51. Which type of gate can be used to add two bits? (a) Ex-OR (b) Ex-NOR (c) Ex-NAND (d) NOR 52. Show from the truth table how an exclusive-OR gate can be used to invert the data on one input if the other input is a special control function. (a) Using A as the control, when A = 0, X is the same as B. When A = 1, X is the same as B. (b) Using A as the control, when A = 0, X is the same as B. When A = 1, X is the inverse of B. (c) Using A as the control, when A = 0, X is the inverse of B. When A = 1, X is the same as B. (d) Using A as the control, when A = 0, X is the inverse of B. When A = 1, X is the inverse of B. 53. Parity systems are defined as either________ or ________ and will add an extra ________ to the digital information being transmitted. (a) positive, negative, byte (b) odd, even, bit (c) upper, lower, digit (d) on, off, decimal 54. The Ex-NOR is sometimes called…
- 101. How many inputs are on the logic gates of a 74HC21 IC? (a) 1 (b) 2 (c) 3 (d) 4 102. What are the pin numbers of the outputs of the gates in a 7432 IC? (a) 3, 6, 10, and 13 (b) 1, 4, 10, and 13 (c) 3, 6, 8, and 11 (d) 1, 4, 8, and 11 103. How many AND gates are found in a 7411 IC? (a) 1 (b) 2 (c) 3 (d) 4 104. Which of the following equations would accurately describe a four-input OR gate when A = 1, B = 1, C = 0, and D = 0? (a) 1 + 1 + 0 + 0 = 01 (b) 1 + 1 + 0 + 0 = 1 (c) 1 + 1 + 0 + 0 = 0 (d) 1 + 1 + 0 + 0 = 00 105. Which of the following logical operations is represented by the + sign in Boolean algebra? (a) inversion (b) AND (c) OR (d) complementation 106. The logic gate that will have HIGH or "1" at its output when any one (or more) of its inputs is HIGH is a(n): (a) OR gate (b)…
- 51. The device shown here is most likely a ________. (a) comparator (b) multiplexer (c) demultiplexer (d) parity generator 52. The device shown here is most likely a ________. (a) comparator (b) multiplexer (c) demultiplexer (d) parity generator 53. For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the input is HIGH. What is the status of the outputs? (a) All are HIGH. (b) All are LOW. (c) All but are LOW. (d) All but are HIGH. 54. A circuit that can convert one of ten numerical keys pressed on a keyboard to BCD is a ________. (a) priority encoder (b) decoder (c) multiplexer (d) demultiplexer 55. What is the indication of a short on the input of a load gate? (a) Only the output of the defective gate is affected. (b) There is a signal loss to all gates on the node. (c) The affected node will be stuck in the LOW state. (d) There is a signal loss to all gates on the node, and the affected node will be stuck in the LOW state. 56. What is the indication of a short to ground in the output of a…
- 151. The following waveform pattern is for a(n) ________. (a) 2-input AND gate (b) 2-input OR gate (c) Exclusive-OR gate (d) None of the above 152. The following waveform pattern is for a(n) ________. (a) 2-input AND gate (b) 2-input OR gate (c) Exclusive-OR gate (d) None of the above 153. The symbol shown represents a(n) ________. (a) AND gate (b) OR gate (c) NAND gate (d) NOR gate 154. The symbol shown represents ________. (a) AND-OR logic (b) AOI logic (c) XOR gate (d) XNOR gate 155. The expression can be directly implemented using only ________. (a) an XOR gate (b) an XNOR gate (c) an AOI circuit (d) three 2-input NAND gates 156. Assume you have A, B, C, and D available but not their complements. The minimum number of 2-input NAND gates required to implement the equation is ________. (a) 3 (b) 4 (c) 5 (d) 6 157. A gate can drive a number of load gate inputs up to its specified ________. (a) supply voltage (b) noise margin (c) fan-in (d) fan-out 158. If both inputs of a 2-input NOR gate are connected, the gate will function as an ________. (a) OR gate (b) AND gate…