5555555555102. Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________. (a) set (b) reset (c) latch (d) toggle
5555555555135. A positive edge-triggered flip-flop will accept inputs only when the clock ________. (a) is LOW (b) changes from HIGH to LOW (c) is HIGH (d) changes from LOW to HIGH
5555555555147. When the output of the NOR gate S-R flip-flop is Q = 0 and , the inputs are: (a) S = 1, R = 1 (b) S = 1, R = 0 (c) S = 0, R = 1 (d) S = 0, R = 0
5555555555109. The asynchronous inputs are normally labeled ________ and ________, and are normally active-________ inputs. (a) PRE, CLR, LOW (b) ON, OFF, HIGH (c) START, STOP, LOW (d) SET, RESET, HIGH